1. Field of the Invention
This invention relates to semiconductor structures wherein crossover connections between active devices within the structure, external leads and power buses are formed on the surface of the semiconductor body.
2. Description of the Prior Art
Recent technological advances have enabled transistor manufacturers to place more and more active and passive elements into the body of a semiconductor chip. For example, it is possible to form more than 500 such elements into a chip having an area of less than 100 by 100 mils. This has presented a serious problem in interconnecting the devices within the chip to form circuits and in providing external connections from the chip.
Several alternative techniques have been advanced, none of which have met with great success.
In one method, the connections are formed separately on multilayered ceramic substrates. With this method, many of the interconnections between individual devices as well as substantially all of the external connections to other sources are formed on the various layers of the laminated ceramic structure. However, this method has the basic flow of consuming a large area as compared to the size of the semiconductor chip mounted thereon. In addition to the basic flaw, there is a problem of the length of the connection between the device within the chip and the connection on the ceramic. The longer the lead, other factors being equal, the longer it will take a signal to propagate. This has led to the rather anomalous result of having the transistor "package" cause a considerable portion of the total delay in signal propagation. Of course, as the art has advanced in forming a device within a smaller area of the semiconductor chip, this problem has grown steadily worse, relatively speaking.
A second technique which has received considerable publicity is the bonding of external connections at the periphery of the chip itself or on a ceramic substrate which holds the chip. These connections, in the form of wires of minute diameter, jump over the active area of the chip, very similarly to conventional wiring. The problems with this technique are the fragility of the wires and the great difficulty in bonding the wires to small contact areas.
A third technique, to which the present invention is directed, is to produce most of the conductive connections in multiple levels on the surface of the chip itself. In circuits requiring relatively few interconnections between devices and few power connections, all of the metallization may be confined to one level. However, the art has progressed to having such increased density of devices per chip that more than one "metallization level is required. In general, the prior art multilevel metallization technique has comprised:
1. the deposition of ohmic contacts and certain device interconnections on a first level;
2. depositing one or more insulation layers atop the first metallization;
3. producing via holes within the insulation;
4. depositing a second pattern of metallization atop the insulation;
5. simultaneously connecting selectively the first level of metallization with the second level through the via holes; and reproducing steps (2), (3), (4), and (5) to form a third level.
This technique, and the many variations of it which have been suggested in the prior art, has resulted in a commercially acceptable transistor structure. However, in production the ratio of acceptable finished circuits to the total number of circuits started initially, i.e., the yield, has remained lower than desired. The basic problem lies in the humps formed by the conductive lands at the locations where an insulation layer passes over or under the conductive lands which form the metallization pattern. These humps are present in all techniques which appear in patents and technical publications directed to insulating the multilevel metallization patterns printed on top of the chip. They are not evident in many drawings, probably for reasons of clarity and because they had not caused noticeable problems in the particular processes or structures involved. However, these humps have been found to be a principal cause of the formation of pinholes and stress cracks in the insulation layer and pinholes in the metallization. One reason for this lies in the discontinuity present in the otherwise smooth insulation layer where it passes over the conductive metallization pattern. The stress on the insulation layer is greatest at that location. In addition, there are locations in a non-planar insulation layer where its thickness is less than the average thickness. These locations will have more pinholes than average. These pinholes and stress cracks may cause one portion of a metallization pattern to "short" with another; or cause one portion of one level of metallization to short with another level. Pinholes and stress cracks in the insulation layer may also cause pinholes in the metallization. During an etching process on the metallization, the etchant may seep through the insulation and attack the metal at an undesired location, resulting in the pinhole. Pinholes in the metal way, in turn, cause pinholes in the insulation layer if an insulation etchant seeps through the metal. Any of these occurrences can cause a defective chip.